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 MP7541B
15 V CMOS Multiplying 12-Bit Digital-to-Analog Converter
FEATURES
* * * * * * * ESD Protection: 2000 V Minimum Full Four Quadrant Multiplication Low Glitch Energy 12-Bit Linearity (End-Point) Guaranteed Monotonic. All Grades. All Temperatures. TTL/5 V CMOS Compatible Stable, More Accurate Segmented Architecture - 2.0 ppm/C Typ. Gain Error Tempco - 0.2 ppm/C Max. Linearity Tempco - Lowest Sensitivity to Output Amplifier Offset * Latch-Up Free
APPLICATIONS
* * * * * * * * Industrial Automation Automatic Test Equipment Disk Drive Servo Systems Digital/Synchro Conversion Programmable Gain Amplifiers Ratiometric A/D Conversion Function Generation Digitally Controlled Filters
GENERAL DESCRIPTION
The MP7541B is a pin-compatible replacement which offers superior performance in latch-up and ESD protection versus the comparable 7541 and 7541A. The high ESD protection will reduce failures caused by mishandling. These devices are manufactured using patented advanced thin film resistors on a double metal CMOS process which result in ultra stable thin film and superior long life reliability and stability. The MP7541B incorporates a bit decoding technique yielding lower glitch, higher
speed and excellent accuracy over temperature and time. The MP7541B's outstanding features are: Stability: Both Integral Non-Linearity (INL) and DifferentialNon-Linearity (DNL) are rated at 0.2 ppm/C maximum. Monotonicity is guaranteed over the entire temperature range. Gain Temperature Coefficient (TCGE) is 2.0 ppm/C typical. Lower Sensitivity to Output Amplifier Offset: Multiplying DACs provide an output current into a virtual ground of the output op amp. Additional linearity error caused by the op amp is reduced by a factor of 3 in the MP7541B versus conventional R-2R DACs.
SIMPLIFIED BLOCK DIAGRAM
VDD 40k 80k "1" "1" "1" "1" "1" "1" 40k 40k 80k RFB 10k IOUT1 VREF Switch Drivers 3-7 Decoder IOUT2
GND BIT 1 BIT 2 (MSB)
BIT 3
BIT 4
BIT 12 (LSB)
Rev. 2.00 1
MP7541B
ORDERING INFORMATION
Package Type
Plastic Dip Plastic Dip SOIC SOIC Ceramic Dip Ceramic Dip
Temperature Range
-40 to +85C -40 to +85C -40 to +85C -40 to +85C -55 to +125C -55 to +125C
Part No.
MP7541BKN MP7541BJN MP7541BKS MP7541BJS MP7541BTD* MP7541BSD*
INL (LSB)
1/2 1 1/2 1 1/2 1
DNL (LSB)
1/2 1 1/2 1 1/2 1
Gain Error (LSB)
5 8 5 8 5 8
*Contact factory for non-compliant military processing
PIN CONFIGURATIONS
See Packaging Section for Package Dimensions
IOUT1 IOUT2 GND (MSB) BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6
1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
RFB VREF VDD BIT 12 (LSB) BIT 11 BIT 10 BIT 9 BIT 8 BIT 7
IOUT1 IOUT2 GND (MSB) BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6
1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
RFB VREF VDD BIT 12 (LSB) BIT 11 BIT 10 BIT 9 BIT 8 BIT 7
18 Pin PDIP, CDIP (0.300") N18, D18
18 Pin SOIC (Jedec, 0.300") S18
PIN OUT DEFINITIONS
PIN NO. 1 2 3 4 5 6 7 8 9 NAME IOUT1 IOUT2 GND BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 DESCRIPTION Current Output 1 Current Output 2 Ground Data Input Bit 1 (MSB) Data Input Bit 2 Data Input Bit 3 Data Input Bit 4 Data Input Bit 5 Data Input Bit 6 PIN NO. 10 11 12 13 14 15 16 17 18 NAME BIT 7 BIT 8 BIT 9 BIT 10 BIT 11 BIT 12 VDD VREF RFB DESCRIPTION Data Input Bit 7 Data Input Bit 8 Data Input Bit 9 Data Input Bit 10 Data Input Bit 11 Data Input Bit 12 (LSB) Positive Power Supply Reference Input Voltage Internal Feedback Resistor
Rev. 2.00 2
MP7541B
ELECTRICAL CHARACTERISTICS
VDD = + 15 V, VREF = +10 V, IOUT1 = IOUT2 = GND = 0 V Unless Otherwise Noted.
Parameter STATIC PERFORMANCE1 Resolution (All Grades) Integral Non-Linearity (Relative Accuracy) K, T J, S Differential Non-Linearity K, T J, S Gain Error K, T J, S Gain Temperature Coefficient2 Power Supply Rejection Ratio N INL +1/2 +1 DNL +1/2 +1 GE +3 +6 TCGE PSRR 5 +50 +5 +8 +2 +100 ppm/C ppm/% Gain/Temperature |Gain/VDD| VDD = + 5% Digital Inputs = 0 or 5 V RL=100, CEXT=13pF tS FT Egl tPD 0.65 1.0 500 60 1.0 s mV p-p nVs ns Full scale change to 1/2 LSB VREF = 20 V p-p 10kHz, Sinewave 00--0 to 11--1 Input Change From 50% of digital input to 10% of final analog output current +1/2 +1 LSB +1/2 +1 LSB All grades monotonic over full temperature range. Using Internal RFB 12 12 Bits LSB End Point Linearity Symbol Min 25C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments
Output Leakage Current DYNAMIC PERFORMANCE2 Current Settling Time AC Feedthrough at IOUT1 Glitch Energy Propagation Delay
ILKG
5
+10
+200
nA
REFERENCE INPUT Input Resistance DIGITAL INPUTS Logical "1" Voltage Logical "0" Voltage Input Leakage Current Input Capacitance2 Data ANALOG OUTPUTS2 Output Capacitance COUT1 COUT1 COUT2 COUT2 POWER SUPPLY3 Functional Voltage Range2 Supply Current VDD IDD 4.5 16 1.0 4.5 16 1.0 V mA 100 50 50 100 pF pF pF pF DAC all 1's DAC all 0's DAC all 1's DAC all 0's VIH VIL IINH, IINL CIN 3.0 2.4 0.8 +1.0 8.0 3.0 0.8 +1.0 8.0 V V A pF RIN 5 10 20 5 20 k
All Digital Inputs = 0 or 5 V
Rev. 2.00 3
MP7541B
ELECTRICAL CHARACTERISTICS (CONT'D)
NOTES:
1 2 3
Full Scale Range (FSR) is 10V for unipolar mode. Guaranteed but not production tested. Specified values guarantee functionality. Refer to other parameters for accuracy.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS (TA = +25C unless otherwise noted)1, 2
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +17 V Digital Input Voltage to GND . . . . GND -0.5 to VDD +0.5 V IOUT1, IOUT2 to GND . . . . . . . . . . . GND -0.5 to VDD +0.5 V VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V VRFB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V Storage Temperature . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 seconds) . . . . . . +300C Package Power Dissipation Rating to 75C CDIP, PDIP, SOIC . . . . . . . . . . . . . . . . . . . . . . . . . 850mW Derates above 75C . . . . . . . . . . . . . . . . . . . . . 11mW/C
NOTES: 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 20mA for less than 100s.
APPLICATION NOTES Refer to Section 8 for Applications Information
PERFORMANCE CHARACTERISTICS
Graph 1. Linearity Error vs. Digital Input Code
Rev. 2.00 4
MP7541B
18 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) S18
D
18
10
E
H
9
h x 45 C Seating Plane e B A1 L A
INCHES SYMBOL A A1 B C D E e H h L MIN 0.097 0.0050 0.014 0.0091 0.451 0.292 MAX 0.104 0.0115 0.019 0.0125 0.461 0.299
MILLIMETERS MIN 2.464 0.127 0.356 0.231 11.46 7.42 MAX 2.641 0.292 0.483 0.318 11.71 7.59
0.050 BSC 0.400 0.010 0.016 0 0.410 0.016 0.035 8
1.27 BSC 10.16 0.254 0.406 0 10.41 0.406 0.889 8
Rev. 2.00 5
MP7541B
18 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP) N18
S
18 1 Q1 D
10 9 E1 E A1
Seating Plane
A L B e B1
C
INCHES SYMBOL A A1 B B1 (1) C D E E1 e L MIN -- 0.015 0.014 0.038 0.008 0.845 0.295 0.220 MAX 0.200 -- 0.023 0.065 0.015 0.925 0.325 0.310
MILLIMETERS MIN -- 0.38 0.356 0.965 0.203 21.46 7.49 5.59 MAX 5.08 -- 0.584 1.65 0.381 23.50 8.26 7.87
0.100 BSC 0.115 0 0.055 0.040 (1) 0.150 15 0.070 0.098
2.54 BSC 2.92 0 1.40 1.02 3.81 15 1.78 2.49
Q1 S Note:
The minimum limit for dimensions B1 may be 0.023" (0.58 mm) for all four corner leads only.
Rev. 2.00 6
MP7541B
18 LEAD CERAMIC DUAL-IN-LINE (300 MIL CDIP) D18
S1 See Note 1
18
S
10
1
9
E1 D Base Plane Seating Plane L e b b1 c L1 Q A E
INCHES SYMBOL A b b1 c D E E1 e L L1 Q S S1 MIN -- 0.014 0.038 0.008 -- 0.220 0.290 MAX 0.200 0.023 0.065 0.015 0.960 0.310 0.320
MILLIMETERS MIN -- 0.356 0.965 0.203 -- 5.59 7.37 MAX 5.08 0.584 1.65 0.381 24.38 7.87 8.13 NOTES -- -- 2 -- 4 4 7 5 -- -- 3 6 6 --
NOTES 1. Index area; a notch or a lead one identification mark is located adjacent to lead one and is within the shaded area shown. 2. The minimum limit for dimension b1 may be 0.023 (0.58 mm) for all four corner leads only. 3. Dimension Q shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic lead spacing is 0.100 inch (2.54 mm) between centerlines. 6. Applies to all four corners. 7. This is measured to outside of lead, not center.
0.100 BSC 0.125 0.150 0.015 -- 0.005 0 0.200 -- 0.070 0.098 -- 15
2.54 BSC 3.18 3.81 0.381 -- 0.13 0 5.08 -- 1.78 2.49 -- 15
Rev. 2.00 7
MP7541B
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1993 EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 2.00 8


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